With a recent trend toward higher integration and higher density in semiconductor devices, circuit interconnects become finer and finer and the number of levels in multilayer interconnect is increasing. In the fabrication process of the multilayer interconnects with finer circuit, as the number of interconnect levels increases, film coverage (or step coverage) of step geometry is lowered in thin film formation because surface steps grow while following surface irregularities on a lower layer. Therefore, in order to fabricate the multilayer interconnects, it is necessary to improve the step coverage and planarize the surface. It is also necessary to planarize semiconductor device surfaces so that irregularity steps formed thereon fall within a depth of focus in optical lithography. This is because finer optical lithography entails shallower depth of focus.
Accordingly, the planarization of the semiconductor device surfaces is becoming more important in the fabrication process of the semiconductor devices. Chemical mechanical polishing (CMP) is the most important technique in the surface planarization. This chemical mechanical polishing is a process of polishing a wafer by bringing the wafer into sliding contact with a polishing surface of a polishing pad while supplying a polishing liquid containing abrasive grains, such as silica (SiO2), onto the polishing surface.
A polishing apparatus for performing CMP has a polishing table that supports the polishing pad thereon, and a substrate holding apparatus, which is called a top ring or a polishing head, for holding a wafer. When the wafer is polished using such polishing apparatus, the substrate holding apparatus holds the wafer and presses it against the polishing surface of the polishing pad at a predetermined pressure, while the polishing table and the substrate holding apparatus are moved relative to each other to bring the wafer into sliding contact with the polishing surface to thereby polish a surface of the wafer.
During polishing of the wafer, if a relative pressing force applied between the wafer and the polishing surface of the polishing pad is not uniform over the entire surface of the wafer, insufficient polishing or excessive polishing would occur depending on a force applied to each portion of the wafer. Thus, in order to make the pressing force against the wafer uniform, the substrate holding apparatus has a pressure chamber defined by an elastic membrane at a lower part thereof. This pressure chamber is supplied with a fluid, such as air, to press the wafer through the elastic membrane with a fluid pressure.
However, since the above-described polishing pad has elasticity, the pressing force becomes non-uniform in an edge portion (or a peripheral portion) of the wafer during polishing of the wafer. Such non-uniform pressing force would result in so-called “rounded edge” which is excessive polishing that occurs only in the edge portion of the wafer. In order to prevent such rounded edge, a retaining ring for retaining the edge portion of the wafer is provided so as to be vertically movable relative to a top ring body (or carrier head body) and to press the polishing surface of the polishing pad around a circumferential edge of the wafer.
As the types of semiconductor devices have been increasing tremendously in recent years, there is an increasing demand for controlling a polishing profile in the wafer edge portion for each device or each CMP process (e.g., an oxide film polishing process and a metal film polishing process). One of the reasons is that each wafer has a different initial film-thickness distribution because a film-forming process, which is performed prior to the CMP process, varies depending on the type of film. Typically, a wafer is required to have a uniform film-thickness distribution over its entire surface after the CMP process. Therefore, different initial film-thickness distributions necessitate different polishing profiles.
Other reason is that types of polishing pads and polishing liquids, both of which are consumables of the polishing apparatus, are increasing greatly from a viewpoint of costs. Use of different polishing pads or different polishing liquids results in greatly different polishing profiles particularly in the wafer edge portion. In a semiconductor device fabrication, the polishing profile in the wafer edge portion can greatly affect a product yield. Therefore, it is very important to precisely control the polishing profile of the wafer edge portion particularly in a narrow area of the wafer edge portion in a radial direction.
In order to control the polishing profile of the wafer edge portion, various elastic membranes as disclosed in Japanese laid-open patent publication No. 2013-111679 have been proposed. However, these elastic membranes are suitable for controlling the polishing profile in a relatively wide area of the wafer edge portion.